A 50-MU-A STANDBY 1MX1/256KX4 CMOS DRAM WITH HIGH-SPEED SENSE AMPLIFIER

被引：7

作者：

FUJII, S

SAITO, S

OKADA, Y

SATO, M

SAWADA, S

SHINOZAKI, S

NATORI, K

OZAWA, O

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1986年 / 21卷 / 05期

关键词：

D O I：

10.1109/JSSC.1986.1052589

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：643 / 648

页数：6

共 8 条

[1] A 64K-DRAM WITH 35 NS STATIC COLUMN OPERATION [J].

BABA, F ;

MOCHIZUKI, H ;

YABU, T ;

SHIRAI, K ;

MIYASAKA, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) :447-451

[2]

INOUE Y, 1985, FEB IEEE INT SOL STA, P238

[3]

KIRSCH HC, 1985, FEB ISSCC, P256

[4] A RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE [J].

KUMANOYA, M ;

FUJISHIMA, K ;

MIYATAKE, H ;

NISHIMURA, Y ;

SAITO, K ;

MATSUKAWA, T ;

YOSHIHARA, T ;

NAKANO, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (05) :909-913

[5] HALF-VDD BIT-LINE SENSING SCHEME IN CMOS DRAMS [J].

LU, NCC ;

CHAO, HH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (04) :451-454

[6] A 1-MBIT CMOS DRAM WITH FAST PAGE MODE AND STATIC COLUMN MODE [J].

SAITO, S ;

FUJII, S ;

OKADA, Y ;

SAWADA, S ;

SHINOZAKI, S ;

NATORI, K ;

OZAWA, O .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (05) :903-908

[7]

SATO K, 1985, FEB ISSCC, P254

[8] A 1-MBIT CMOS DYNAMIC RAM WITH A DIVIDED BITLINE MATRIX ARCHITECTURE [J].

TAYLOR, RT ;

JOHNSON, MG .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (05) :894-902

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