A 1-MBIT CMOS DYNAMIC RAM WITH A DIVIDED BITLINE MATRIX ARCHITECTURE

被引：10

作者：

TAYLOR, RT

JOHNSON, MG

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1985年 / 20卷 / 05期

关键词：

D O I：

10.1109/JSSC.1985.1052412

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：894 / 902

页数：9

共 21 条

[1]

Bayless M., 1983, International Electron Devices Meeting 1983. Technical Digest, P250

[2] A 256K DYNAMIC RANDOM-ACCESS MEMORY [J].

BENEVIT, CA ;

CASSARD, JM ;

DIMMLER, KJ ;

DUMBRI, AC ;

MOUND, MG ;

PROCYK, FJ ;

ROSENZWEIG, W ;

YANOF, AW .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (05) :857-862

[3]

DUTTON D, 1982, TARGET SPECIFICATION

[4]

EATON SS, 1982, ELECTRONICS 0324, P132

[5] A FAULT-TOLERANT 30 NS-375 MW 16KX1 NMOS STATIC RAM [J].

HARDEE, KC ;

SUD, R .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (05) :435-443

[6]

Harrington T., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P71

[7]

HUDSON EL, 1982, ISSCC, P248

[8]

ITOH K, 1984, ISSCC, P282

[9]

JONES F, 1981, APR ELECTRO

[10] A 60 NS 256KX1 BIT DRAM USING LD3 TECHNOLOGY AND DOUBLE-LEVEL METAL INTERCONNECTION [J].

KERTIS, RA ;

FITZPATRICK, KJ ;

OHRI, KB .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (05) :585-590

← 1 2 3 →