LOW-COST AND LOW-POWER SILICON NPN BIPOLAR PROCESS WITH NMOS TRANSISTORS (ADRF) FOR RF AND MICROWAVE APPLICATIONS

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5,5-V BVCEO, optional 0.7-mu m (L(eff)) NMOS transistors with p(+) polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p(+) polysilicon-to-n(+) plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes, Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.