PROCESS AND DEVICE PERFORMANCE OF SUBMICROMETER-CHANNEL CMOS DEVICES USING DEEP-TRENCH ISOLATION AND SELF-ALIGNED TISI2 TECHNOLOGIES

被引：13

作者：

YAMAGUCHI, T

MORIMOTO, S

PARK, HK

EIDEN, GC

机构：

来源：

关键词：

D O I：

10.1109/T-ED.1985.21928

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：184 / 193

页数：10

共 15 条

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[8] A TRANSMISSION-LINE MODEL FOR SILICIDED DIFFUSIONS - IMPACT ON THE PERFORMANCE OF VLSI CIRCUITS
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[9] AN OPTIMALLY DESIGNED PROCESS FOR SUBMICROMETER MOSFETS
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[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (05) : 925 - 931