A PROCEDURE FOR FIELD IMPLANTING A CMOS ISOPLANAR INTEGRATED-CIRCUIT

被引:1
作者
HARPER, F
机构
关键词
D O I
10.1109/T-ED.1985.22007
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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页码:720 / 722
页数:3
相关论文
共 9 条
[1]  
BOLEKY E, 1977, Patent No. 4012383
[2]  
DEAL B, 1977, Patent No. 4027380
[3]  
LIU CM, 1982, MAY IEEE CUST INT CI
[4]   HIGH-DENSITY AND REDUCED LATCHUP SUSCEPTIBILITY CMOS TECHNOLOGY FOR VLSI [J].
MANOLIU, J ;
TSENG, FH ;
WOO, BJ ;
MEIER, TJ .
IEEE ELECTRON DEVICE LETTERS, 1983, 4 (07) :233-235
[5]   SILICON-GATE N-WELL CMOS PROCESS BY FULL ION-IMPLANTATION TECHNOLOGY [J].
OHZONE, T ;
SHIMURA, H ;
TSUJI, K ;
HIRAO, T .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (09) :1789-1795
[6]   A RETROGRADE P-WELL FOR HIGHER DENSITY CMOS [J].
RUNG, RD ;
DELLOCA, CJ ;
WALKER, LG .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1981, 28 (10) :1115-1119
[7]  
RUNG RD, 1982, IEDM
[8]   SURFACE INDUCED LATCHUP IN VLSI CMOS CIRCUITS [J].
TAKACS, D ;
WERNER, C ;
HARTER, J ;
SCHWABE, U .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (03) :279-286
[9]   HMOS-CMOS - A LOW-POWER HIGH-PERFORMANCE TECHNOLOGY [J].
YU, K ;
CHWANG, RJC ;
BOHR, MT ;
WARKENTIN, PA ;
STERN, S ;
BERGLUND, CN .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (05) :454-459