PRACTICAL REDUCTION OF DISLOCATION DENSITY IN SIMOX WAFERS

被引：44

作者：

NAKASHIMA, S

IZUMI, K

机构：

[1] NTT LSI Laboratories, Atsugi, 3-1 Morinosato Wakamiya

来源：

ELECTRONICS LETTERS | 1990年 / 26卷 / 20期

关键词：

Semiconductor devices and materials; Silicon;

D O I：

10.1049/el:19901055

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The dislocation density in the superficial silicon layers of SIMOX wafers formed under different oxygen implantation conditions has been investigated using a Secco etching technique. An extremely low dislocation density in the order of 102 cm-2 has been obtained for wafers implanted at 180keV with a dose of 0.4 x 1018 and doses ranging from 0.9 to 1.2 x 1018O+/cm2 at a wafer temperature of 550°C followed by post-implant anneal at temperatures higher than 1300°C. The buried oxide layers of these SIMOX wafers have breakdown voltages higher than 40 V. © 1990, The Institution of Electrical Engineers. All rights reserved.

引用

页码：1647 / 1649

页数：3

共 4 条

[1]

AUBERTONHERVE AJ, 1990, 4TH P INT S SOI TECH, V90, P455

[2] CMOS DEVICES FABRICATED ON BURIED SIO2 LAYERS FORMED BY OXYGEN IMPLANTATION INTO SILICON [J].