YIELD ESTIMATION MODEL FOR VLSI ARTWORK EVALUATION

被引:80
作者
MALY, W
DESZCZKA, J
机构
关键词
D O I
10.1049/el:19830156
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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页码:226 / 227
页数:2
相关论文
共 6 条
[1]  
LINSAY BW, 1975, JUN P DES AUT C, P389
[2]  
MEAD C, 1980, INTRO VLSI SYSTEMS, P47
[3]   COST-SIZE OPTIMA OF MONOLITHIC INTEGRATED CIRCUITS [J].
MURPHY, BT .
PROCEEDINGS OF THE IEEE, 1964, 52 (12) :1537-&
[4]  
PAPOULIS A, 1965, PROBABILITY RANDOM V, P71
[5]   DETERMINING IC LAYOUT RULES FOR COST MINIMIZATION [J].
RUNG, RD .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (01) :35-43
[6]  
SCHNITZER AP, 1980, SPIE, V221, P132