DETERMINING IC LAYOUT RULES FOR COST MINIMIZATION

被引：12

作者：

RUNG, RD

机构：

来源：

关键词：

D O I：

10.1109/JSSC.1981.1051533

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：35 / 43

页数：9

共 25 条

[1]

BRADY DD, 1978, ELECTRON DES, V26, P134

[2]

DINGWALL AGF, 1968, OCT P IEEE INT EL DE

[3]

Evans D. H., 1975, Journal of Quality Technology, V7, P1

[4]

Evans D. H., 1974, Journal of Quality Technology, V6, P188

[5]

Evans D. H., 1975, Journal of Quality Technology, V7, P72

[6] DEFECT ANALYSIS AND YIELD DEGRADATION OF INTEGRATED-CIRCUITS [J].

GUPTA, A ;

PORTER, WA ;

LATHROP, JW .

[7] YIELD ANALYSIS OF LARGE INTEGRATED CIRCUIT CHIPS [J].

GUPTA, A ;

LATHROP, JW .

[8]

HU SM, 1979, SOLID STATE ELECTRON, V22, P205, DOI 10.1016/0038-1101(79)90114-X

[9]

IPRI AC, 1977, RCA REV, V38, P323

[10]

IPRI AC, 1979, SOLID STATE TECHNOL, V22, P85