PERFORMANCE TRADE-OFFS IN A PARALLEL TEST-GENERATION FAULT SIMULATION ENVIRONMENT

As parallel processing hardware becomes more common and affordable, multiprocessors are being increasingly used to accelerate VLSI CAD algorithms. The problem of partitioning faults in a parallel test generation/fault simulation (TG/FS) environment has received very little attention in the past. In a parallel TG/FS environment, the fault partitioning method used can have a significant effect on the overall test length and speedup. We propose heuristics to partition faults for parallel test generation with minimization of both the overall run time and test length as an objective. Also, for efficient utilization of available processors, the work load has to be balanced at all times. Since it is very difficult to predict how difficult it will be to generate a test for a particular fault, we propose a load balancing method which uses static partitioning initially and then uses dynamic allocation of work for processors which become idle. We present a theoretical model to predict the performance of the parallel TG/FS process. Finally, we present experimental results based on an implementation on the Intel iPSC/2 hypercube multiprocessor using the ISCAS combinational benchmark circuits.