It is appealing to contemplate how VLSI or wafer-scale integrated systems incorporating free-space optical interconnection might outperform purely electrically interconnected systems. One important dimension of this question concerns the limits that optical physics imposes on the interconnect density of these systems: what bounds can be placed on the physical volume of an optical system that implements a particular interconnect? Another primary consideration ar ises when optical sources and detectors are integrated with circuit substrates, and the substrates are interconnected optically. Because the input and output planes of the optical interconnect are coincident with the substrates themselves, the underlying physical optical constraints are coupled with new considerations driven by circuit a,ld packaging technology, namely, speed, power, circuit integration density, and concurrency of operation. Thus the overall optoelectronic integrated system must be treated as a whole and means sought by which optimal designs can be achieved. This paper first provides a uniform treatment of a general class of optical interconnects based on a Fourier-plane imaging system with an army of soul ces in the object plane and an ari ay of receptors in the image plane. Sources correspond to data outputs of processing ''cells,'' and receptors to their data inputs. A general abstract optical imaging model, capable of representing a large class of real systems, is analyzed to yield constructive upper bounds on system volume that are comparable to those arising from ''3-D VLSI'' computational models. These bounds, coupled with technologically derived constraints, form the heart of a design methodology for optoelectronic systems that uses electronic and optical elements each to their greatest advantage, and exploits the available spatial volume and power in the most efficient way. Many of these concepts are embodied in a demonstration project that seeks to implement a bit-serial, multiprocessing system with a radix-2 butterfly topology, and incorporates various new technology developments. The choice of a butterfly for a demonstration vehicle highlights the benefits of using free-space optics to inter-connect high-wire-area topologies. The practice of wafer-scale integration has been hindered by the large area overhead required by sparing strategies invoked against the inevitable fabrication defects. If wafers are partitioned into functional circuit cells which are then interconnected strictly optically, then defective cells can be accommodated in a wafer-specific diffractive interconnect, with no substrate area lost to inlet-cell connectivity. The task of this interconnect is to map a desired network topology onto the physical set of functional cells. Results of mapping regular processor topologies onto wafers with defective cells are given in terms of asymptotic volume complexity.
