HIGH-SPEED GAAS FREQUENCY-DIVIDERS USING A SELF-ALIGNED DUAL-LEVEL DOUBLE LIFT-OFF SUBSTITUTION GATE MESFET PROCESS

被引：8

作者：

CHANG, MF

LEE, SJ

WALTON, ER

LEE, CP

RYAN, FJ

VAHRENKAMP, RP

KIRKPATRICK, CG

机构：

来源：

IEEE ELECTRON DEVICE LETTERS | 1985年 / 6卷 / 06期

关键词：

D O I：

10.1109/EDL.1985.26125

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：279 / 281

页数：3

共 10 条

[1] HIGH-FREQUENCY DIVIDER CIRCUITS USING ION-IMPLANTED GAAS-MESFETS [J].

ANDRADE, T ;

ANDERSON, JR .

IEEE ELECTRON DEVICE LETTERS, 1985, 6 (02) :83-85

[2]

CATHELIN M, 1980, IEEE P 1, V127

[3]

Flahive P. G., 1984, GaAs IC Symposium Technical Digest 1984 (Cat. No. 84CH2065-1), P7

[4] SELF-ALIGNED SUB-MICRON GATE DIGITAL GAAS INTEGRATED-CIRCUITS [J].

LEVY, HM ;

LEE, RE .

IEEE ELECTRON DEVICE LETTERS, 1983, 4 (04) :102-104

[5] HIGH-TRANSCONDUCTANCE SELF ALIGNED GAAS-MESFET USING IMPLANTATION THROUGH AN AIN LAYER [J].

ONODERA, H ;

YOKOYAMA, N ;

KAWATA, H ;

NISHI, H ;

SHIBATOMI, A .

ELECTRONICS LETTERS, 1984, 20 (01) :45-47

[6] GAAS MESFET LOGIC WITH 4-GHZ CLOCK RATE [J].

VANTUYL, RL ;

LIECHTI, CA ;

LEE, RE ;

GOWEN, E .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1977, 12 (05) :485-496

[7] HIGH-SPEED GAAS DIGITAL INTEGRATED-CIRCUIT WITH CLOCK FREQUENCY OF 4-1 GHZ [J].

YAMAMOTO, R ;

HIGASHISAKA, A .

ELECTRONICS LETTERS, 1981, 17 (08) :291-292

[8] BELOW 20 PS GATE OPERATION WITH GAAS SAINT FETS AT ROOM-TEMPERATURE [J].

YAMASAKI, K ;

YAMANE, Y ;

KURUMADA, K .

ELECTRONICS LETTERS, 1982, 18 (14) :592-593

[9] SELF-ALIGN IMPLANTATION FOR N+-LAYER TECHNOLOGY (SAINT) FOR HIGH-SPEED GAAS ICS [J].

YAMASAKI, K ;

ASAI, K ;

MIZUTANI, T ;

KURUMADA, K .

ELECTRONICS LETTERS, 1982, 18 (03) :119-121

[10]

YOKOYAMA N, 1983, FEB ISCC, V44

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