EFFECT OF HIGH-TEMPERATURE ANNEAL ON INTERFACE STATES GENERATION IN STRESSED METAL-OXIDE-SEMICONDUCTOR DEVICES

Polycrystalline silicon gate metal-oxide-semiconductor transistors, fabricated with polycrystalline silicon leads, were repeatedly electrically stressed by constant-current Fowler-Nordheim tunneling cycles. After every stress cycle the devices were annealed for various time intervals at 950-degrees-C. Capacitance-voltage measurements were used to detect stress-related interface-state generation rates and saturation values. It was found that although the stress-generated interface states are totally annealed by the thermal treatment, their generation rates and saturation values after anneal are a strong function of the anneal time, significantly exceeding the values of the fresh devices and inversely dependent on the anneal time. From the results it is concluded that a new type of latent interface-state sites is generated by the combination of tunneling stress and high-temperature annealing.