EFFECTS OF A NEW TRENCH-ISOLATED TRANSISTOR USING SIDEWALL GATES

被引：7

作者：

HIEDA, K

HORIGUCHI, F

WATANABE, H

SUNOUCHI, K

INOUE, I

HAMAMOTO, T

机构：

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1989年 / 36卷 / 09期

关键词：

D O I：

10.1109/16.34221

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1615 / 1619

页数：5

共 9 条

[1]

Iizuka T., 1981, International Electron Devices Meeting, P380

[2]

Kurosawa K., 1981, International Electron Devices Meeting, P384

[3]

Nakajima S., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P240

[4]

Sawada S., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P778

[5] 3-DIMENSIONAL SIMULATION OF INVERSE NARROW-CHANNEL EFFECT [J].

SHIGYO, N ;

KONAKA, M ;

DANG, RLM .

ELECTRONICS LETTERS, 1982, 18 (06) :274-275

[6]

SHIGYO N, 1987, IEDM, P636

[7] AN EMPIRICAL-MODEL FOR DEVICE DEGRADATION DUE TO HOT-CARRIER INJECTION [J].

TAKEDA, E ;

SUZUKI, N .

IEEE ELECTRON DEVICE LETTERS, 1983, 4 (04) :111-113

[8]

Wada M., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P244

[9] NONPLANAR OXIDATION AND REDUCTION OF OXIDE LEAKAGE CURRENTS AT SILICON CORNERS BY ROUNDING-OFF OXIDATION [J].

YAMABE, K ;

IMAI, K .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (08) :1681-1687

← 1 →