DRAIN-INDUCED BARRIER-LOWERING ANALYSIS IN VLSI MOSFET DEVICES USING TWO-DIMENSIONAL NUMERICAL SIMULATIONS

被引：56

作者：

CHAMBERLAIN, SG

RAMANAN, S

机构：

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1986年 / 33卷 / 11期

关键词：

D O I：

10.1109/T-ED.1986.22737

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1745 / 1753

页数：9

共 23 条

[1] CAD MODEL FOR THRESHOLD AND SUBTHRESHOLD CONDUCTION IN MOSFETS [J].

ANTOGNETTI, P ;

CAVIGLIA, DD ;

PROFUMO, E .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (03) :454-458

[2]

CHAMBERLAIN SG, 1986, MAY P IEEE CUST INT, P211

[3] THRESHOLD VOLTAGE FROM NUMERICAL SOLUTION OF 2-DIMENSIONAL MOS-TRANSISTOR [J].

DELAMONEDA, FH .

IEEE TRANSACTIONS ON CIRCUIT THEORY, 1973, CT20 (06) :666-673

[4]

Demoulin E., 1977, Proceedings of the NATO Advanced Study Institute on Process and Device Modelling for Integrated Circuit Design, P617

[5] 1 MU-M MOSFET VLSI TECHNOLOGY .2. DEVICE DESIGNS AND CHARACTERISTICS FOR HIGH-PERFORMANCE LOGIC APPLICATIONS [J].

DENNARD, RH ;

GAENSSLEN, FH ;

WALKER, EJ ;

COOK, PW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (04) :325-333

[6] SURFACE CONDUCTION IN SHORT-CHANNEL MOS DEVICES AS A LIMITATION TO VLSI SCALING [J].

EITAN, B ;

FROHMANBENTCHKOWSKY, D .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1982, 29 (02) :254-266

[7]

FU JS, 1984, IEEE T ELECTRON DEV, V31, P440, DOI 10.1109/T-ED.1984.21548

[8] NONPLANAR VLSI DEVICE ANALYSIS USING THE SOLUTION OF POISSON EQUATION [J].

GREENFIELD, JA ;

DUTTON, RW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) :1520-1532

[9] A PARAMETRIC SHORT-CHANNEL MOS-TRANSISTOR MODEL FOR SUBTHRESHOLD AND STRONG INVERSION CURRENT [J].

GROTJOHN, T ;

HOEFFLINGER, B .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (01) :100-112

[10]

HUSSAIN A, 1982, IEEE T ELECTRON DEVI, V29, P631

← 1 2 3 →