SORTING-BASED VLSI ARCHITECTURES FOR THE M-ALGORITHM AND T-ALGORITHM TRELLIS DECODERS

被引：32

作者：

BENGOUGH, PA ^{[1
]}

SIMMONS, SJ ^{[1
]}

机构：

[1] QUEENS UNIV, DEPT ELECT & COMP ENGN, KINGSTON, ON, CANADA

来源：

IEEE TRANSACTIONS ON COMMUNICATIONS | 1995年 / 43卷 / 2-4期

基金：

加拿大自然科学与工程研究理事会;

关键词：

D O I：

10.1109/26.380070

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The well-known M-algorithm and the newer T-algorithm are two closely related reduced-complexity trellis-search algorithms that can be used for data sequence estimation in digital communication systems. VLSI implementations of these algorithms are attractive due to the parallelism and simplicity of their operation. While a small number of VLSI structures have been proposed previously, this paper describes new sorting-based architectures that can be used to realize these algorithms. Specifically, schemes based on odd-even transposition, insertion, and weavesorting techniques are presented. Structures are evaluated on the basis of area, time, and power measures. Actual VLSI implementations have been used to verify timing models.

引用

页码：514 / 522

页数：9

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