Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation

被引：14

作者：

Moreau, Y ^{[1
]}

Duzellier, S ^{[1
]}

Gasiot, J ^{[1
]}

机构：

[1] CERT,ONERA,F-31055 TOULOUSE,FRANCE

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1995年 / 42卷 / 06期

关键词：

D O I：

10.1109/23.488780

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Upsets caused by incident heavy ion on CMOS static RAM are studied here. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined.

引用

收藏

页码：1789 / 1796

页数：8

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