3-DIMENSIONAL SIMULATION OF CHARGE COLLECTION AND MULTIPLE-BIT UPSET IN SI DEVICES

In this paper, three-dimensional numerical simulation is used to explore the basic charge-collection mechanisms in silicon n(+)/p diodes. For diodes on lightly-doped substrates (<1x10(15) cm(-3)) struck by a 100-MeV Fe ion, the funneling effect is very strong and essentially all collection is by funnel-assisted drift. This drift collection may occur as late as several nanoseconds after the strike, later than is usually associated with drift collection. For moderately doped substrates (=1x10(16) cm(-3)) and epitaxial structures grown on heavily-doped substrates, the funnel effect is weaker and drift and diffusion are of more equal importance. For 5-MeV He (alpha-particle) strikes with low-density charge tracks, the charge-collection transient exhibits both drift and diffusion regimes regardless of the substrate doping. Simulations of diodes with passive external loads indicate that while the current response is altered considerably by the load, total collected charge is not greatly affected for the simple resistive loads studied. Three-dimensional mixed-mode simulation is performed to investigate charge-collection behavior and upset mechanisms in complete CMOS SRAM cells. Simulations of double SRAM cell structures indicate that only collection by diffusion from ''between-node'' strikes is capable of producing multiple-bit upsets in the simulated technology. Limitations of the simulations, specifically carrier-carrier scattering models and large concentration gradients, are also discussed.