A GALLIUM-ARSENIDE CONFIGURABLE CELL ARRAY USING BUFFERED FET LOGIC

被引：10

作者：

DEMING, RN

ZUCCA, R

VAHRENKAMP, RP

HOU, LD

NAUSED, BA

GILBERT, BK

机构：

[1] MAYO FDN,SPECIAL PURPOSE PROC DEV GRP,ROCHESTER,MN 55905

[2] ROCKWELL INT CORP,CTR MICROELECTR RES & DEV,THOUSAND OAKS,CA 91360

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1984年 / 19卷 / 05期

关键词：

D O I：

10.1109/JSSC.1984.1052215

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：728 / 738

页数：11

共 14 条

[1] BIPOLAR CIRCUIT-DESIGN FOR A 5000-CIRCUIT VLSI GATE ARRAY [J].

DANSKY, AH .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1981, 25 (2-3) :116-125

[2]

KINELL O, 1982, NOV P IEEE GAAS IC S, P17

[3]

LEE CP, 1982, IEEE GAAS IC S, P169

[4] A HIGH-SPEED LSI GAAS 8BY8-BIT PARALLEL MULTIPLIER [J].

LEE, FS ;

KAELIN, GR ;

WELCH, BM ;

ZUCCA, R ;

SHEN, E ;

ASBECK, P ;

LEE, CP ;

KIRKPATRICK, CG ;

LONG, SI ;

EDEN, RC .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (04) :638-647

[5]

LEE G, 1983, P IEEE GAAS IC S, P174

[6]

LEICHTI CA, 1982, AFWALTR811092 AV LAB, P72

[7]

LIECHTI CA, 1982, IEEE T ELECTRON DEV, V29, P1094

[8]

LONG SI, 1982, P IEEE, V70

[9] A GAAS 16X16 BIT PARALLEL MULTIPLIER [J].

NAKAYAMA, Y ;

SUYAMA, K ;

SHIMIZU, H ;

YOKOYAMA, N ;

OHNISHI, H ;

SHIBATOMI, A ;

ISHIKAWA, H .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) :599-603

[10]

NOBUYUKI T, 1982, 14TH P C SOL STAT DE, P345

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