A CIRCUIT TECHNOLOGY FOR SUB-10-NS ECL 4-MB BICMOS DRAMS

被引：7

作者：

KAWAHARA, T ^{[1
]}

KAWAJIRI, Y ^{[1
]}

KITSUKAWA, G ^{[1
]}

NAKAGOME, Y ^{[1
]}

SAGARA, K ^{[1
]}

KAWAMOTO, Y ^{[1
]}

AKIBA, T ^{[1
]}

KATO, S ^{[1
]}

KAWASE, Y ^{[1
]}

ITOH, K ^{[1
]}

机构：

[1] HITACHI DEVICE ENGN CORP,MOBARA,CHIBA 297,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 11期

关键词：

D O I：

10.1109/4.98968

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Five circuit techniques are proposed to realize sub-10-ns ECL 4-Mb BiCMOS DRAM's. They are the internal power supply voltage scheme using on-chip voltage limiters, an ECL DRAM address buffer with a reset function and level converter, a current source for address buffers compensated for device parameter fluctuation, an overdrive rewrite amplifier for realizing a fast cycle time, and a double-stage current sensing for the main amplifier and output buffer. Using these circuit techniques, an access time of 7.8 ns is expected with a supply current of 198 mA at a 16-ns cycle time.

引用

页码：1530 / 1537

页数：8

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