LATCH AND HOT-ELECTRON GATE CURRENT IN ACCUMULATION-MODE SOI P-MOSFETS

被引：7

作者：

FLANDRE, D ^{[1
]}

CRISTOLOVEANU, S ^{[1
]}

机构：

[1] ENSERG,INPG,CNRS,PHYS COMPOSANTS SEMICOND LAB,F-38016 GRENOBLE,FRANCE

来源：

IEEE ELECTRON DEVICE LETTERS | 1994年 / 15卷 / 05期

关键词：

D O I：

10.1109/55.291601

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Simultaneous measurements of drain and gate currents in short-channel accumulation-mode SOI p-MOSFET'MOs demonstrate that a latch mechanism may occur in these devices and induce an anomalous behavior of the hot-electron gate current: distortion of I(g)(V(g)) curves, hysteresis and excessively high gate current values. 2-D MEDICI simulations based on the lucky-electron model qualitatively reproduce the measurements in the latch regime, and explain the unusual gate current dependence on drain and gate biases. The results are of relevance for reliability and modeling issues.

引用

页码：157 / 159

页数：3

共 16 条

[1]

ACOVIC A, 1992, P IEEE INT SOI C PON, P134

[2] DEGRADATION IN THIN-FILM SOI MOSFETS CAUSED BY SINGLE-TRANSISTOR LATCH [J].

BUNYAN, RJT ;

UREN, MJ ;

THOMAS, NJ ;

DAVIS, JR .

IEEE ELECTRON DEVICE LETTERS, 1990, 11 (09) :359-361

[3] SINGLE-TRANSISTOR LATCH IN SOI MOSFETS [J].

CHEN, CED ;

MATLOUBIAN, M ;

SUNDARESAN, R ;

MAO, BY ;

WEI, CC ;

POLLACK, GP .

IEEE ELECTRON DEVICE LETTERS, 1988, 9 (12) :636-638

[4] HOT-ELECTRON-INDUCED DEGRADATION OF FRONT AND BACK CHANNELS IN PARTIALLY AND FULLY DEPLETED SIMOX MOSFETS [J].

CRISTOLOVEANU, S ;

GULWADI, SM ;

IOANNOU, DE ;

CAMPISI, GJ ;

HUGHES, HL .

IEEE ELECTRON DEVICE LETTERS, 1992, 13 (12) :603-605

[5]

FAYNOT AJ, 1992, 22ND P ESSDERC LEUV, P807

[6] EXTENDED THEORETICAL-ANALYSIS OF THE STEADY-STATE LINEAR BEHAVIOR OF ACCUMULATION-MODE, LONG-CHANNEL P-MOSFETS ON SOI SUBSTRATES [J].

FLANDRE, D ;

TERAO, A .

SOLID-STATE ELECTRONICS, 1992, 35 (08) :1085-1092

[7] DEMONSTRATION OF THE POTENTIAL OF ACCUMULATION-MODE MOS-TRANSISTORS ON SOI SUBSTRATES FOR HIGH-TEMPERATURE OPERATION (150-300-DEGREES-C) [J].

FLANDRE, D ;

TERAO, A ;

FRANCIS, P ;

GENTINNE, B ;

COLINGE, JP .

IEEE ELECTRON DEVICE LETTERS, 1993, 14 (01) :10-12

[8] A LATCH PHENOMENON IN BURIED N-BODY SOI NMOSFET [J].

GAUTIER, J ;

AUBERTONHERVE, AJ .

IEEE ELECTRON DEVICE LETTERS, 1991, 12 (07) :372-374

[9] HOT-CARRIER CURRENT MODELING AND DEVICE DEGRADATION IN SURFACE-CHANNEL P-MOSFETS [J].

ONG, TC ;

KO, PK ;

HU, CM .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1990, 37 (07) :1658-1666

[10]

OUISSE T, 1992, 22ND P ESSDERC LEUV, P473

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