PROCESS AND DEVICE PERFORMANCE OF SUBMICROMETER-CHANNEL CMOS DEVICES USING DEEP-TRENCH ISOLATION AND SELF-ALIGNED TISI2 TECHNOLOGIES

A deeper n-well has been found to allow for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FETs. The deep n-well, however, requires a large space between n-channel and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSIs. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6- mu m-deep with 2- mu m-wide deep trench is etched in the epitaxial layer and is refilled with 1500 angstrom of thermal silicon-dioxide film and 2 mu m of polysilicon film. The sheet resistances of N** plus and P** plus diffusion and N** plus -doped polysilicon layers were reduced to 3 to 4 OMEGA / D'ALEMB by using the self-aligned TiSi//2 layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n-channel and p-channel MOSFETs was improved approximately 33 to 37% compared with conventional MOSFETs without the self-aligned TiSi//2 layer. The 0. 5- mu m-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi//2 layer operated at a propagation delay time of 140 ps with a power dissipation of 1. 1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static divided by counter without suffering from latchup even at the latchup trigger current of 200 mA.