OPTIMIZATION OF SIDEWALL MASKED ISOLATION PROCESS

被引：5

作者：

TENG, CW

POLLACK, G

HUNTER, WR

机构：

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1985年 / 32卷 / 02期

关键词：

D O I：

10.1109/T-ED.1985.21921

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：124 / 131

页数：8

共 15 条

[1]

APPELS JA, 1970, PHILIPS RES REP, V25, P118

[2]

Chen J. Y., 1982, International Electron Devices Meeting. Technical Digest, P233

[3]

CHIU KY, 1982, IEEE T ELECTRON DEV, V29, P536, DOI 10.1109/T-ED.1982.20739

[4] ELECTRICAL PERFORMANCE AND PHYSICS OF ISOLATION REGION STRUCTURES FOR VLSI [J].

GOODWIN, SH ;

PLUMMER, JD .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (07) :861-872

[5]

Grove A S, 1967, PHYS TECHNOLOGY SEMI

[6]

HUI JCH, 1982, IEEE T ELECTRON DEV, V29, P554

[7]

Iizuka T., 1981, International Electron Devices Meeting, P380

[8] A NEW DIELECTRIC ISOLATION METHOD USING POROUS SILICON [J].

IMAI, K .

SOLID-STATE ELECTRONICS, 1981, 24 (02) :159-&

[9] DISLOCATION GENERATION AT SI3N4 FILM EDGES ON SILICON SUBSTRATES AND VISCOELASTIC BEHAVIOR OF SIO2-FILMS [J].

ISOMAE, S ;

TAMAKI, Y ;

YAJIMA, A ;

NANBA, M ;

MAKI, M .

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1979, 126 (06) :1014-1019

[10] SELECTIVE POLYSILICON OXIDATION TECHNOLOGY FOR VLSI ISOLATION [J].

MATSUKAWA, N ;

NOZAWA, H ;

MATSUNAGA, J ;

KOHYAMA, S .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1982, 29 (04) :561-567

← 1 2 →