A 1 GHZ 50 MW GAAS DUAL MODULUS DIVIDER IC

被引:1
作者
SHIMIZU, S
KAMATANI, Y
TOYODA, N
KANAZAWA, K
MOCHIZUKI, M
TERADA, T
HOJO, A
机构
[1] Toshiba Research & Development, Cent, Kawasaki, Jpn, Toshiba Research & Development Cent, Kawasaki, Jpn
关键词
ELECTRONIC CIRCUITS; FREQUENCY DIVIDING - FREQUENCY SYNTHESIZERS - Components - LOGIC DESIGN - Computer Aids - SEMICONDUCTOR DEVICES - Applications - TRANSISTORS; FIELD EFFECT;
D O I
10.1109/JSSC.1984.1052212
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 1 GHz 50 mw GaAs dual modulus divider IC has been realized by using source-coupled FET logic. Dividing values are 128/129 and 64/65. The chip size is 0. 94 multiplied by 1. 07 mm, in which 223 FET's, 101 diodes, and 80 resistors are integrated. The process used in the IC fabrication is the platinum (Pt) buried gate planar FET process. The maximum toggle frequency was 1. 12 GHz and IC current was 9. 55 mA at 5 v supply voltage. About 10-30 percent chip yield was achieved in the wide (0. 1-0. 4) EFET threshold voltage range.
引用
收藏
页码:710 / 715
页数:6
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