AN ANALYTIC MODEL TO ESTIMATE THE AVALANCHE BREAKDOWN VOLTAGE IMPROVEMENT FOR LDD DEVICES

被引：9

作者：

LAI, FS

机构：

来源：

SOLID-STATE ELECTRONICS | 1985年 / 28卷 / 10期

关键词：

D O I：

10.1016/0038-1101(85)90026-7

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：959 / 965

页数：7

共 12 条

[1] DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].

DENNARD, RH ;

GAENSSLEN, FH ;

YU, HN ;

RIDEOUT, VL ;

BASSOUS, E ;

LEBLANC, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268

[2] SIMPLE 2-DIMENSIONAL MODEL FOR IGFET OPERATION IN SATURATION REGION [J].

ELMANSY, YA ;

BOOTHROYD, AR .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1977, 24 (03) :254-262

[3]

HSU FC, 1982, IEEE T ELECTRON DEV, V29, P1735

[4]

LAI FS, 1984, 166TH EL SOC M REC N

[5]

MULLER RS, 1977, DEVICE ELECTRONICS I

[6] DESIGN AND CHARACTERISTICS OF THE LIGHTLY DOPED DRAIN-SOURCE (LDD) INSULATED GATE FIELD-EFFECT TRANSISTOR [J].

OGURA, S ;

TSANG, PJ ;

WALKER, WW ;

CRITCHLOW, DL ;

SHEPARD, JF .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) :1359-1367

[7]

SUN E, 1978, IEDM, P478

[8] AN AS-P(N+-N-) DOUBLE DIFFUSED DRAIN MOSFET FOR VLSIS [J].

TAKEDA, E ;

KUME, H ;

NAKAGOME, Y ;

MAKINO, T ;

SHIMIZU, A ;

ASAI, S .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1983, 30 (06) :652-657

[9] CORRELATION BETWEEN SUBSTRATE AND GATE CURRENTS IN MOSFETS [J].

TAM, S ;

KO, PK ;

HU, CM ;

MULLER, RS .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1982, 29 (11) :1740-1744

[10] ONE-DIMENSIONAL WRITING MODEL OF N-CHANNEL FLOATING GATE IONIZATION-INJECTION MOS (FIMOS) [J].

TANAKA, S ;

ISHIKAWA, M .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1981, 28 (10) :1190-1197

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