BARRIER MODE BEHAVIOR OF A JUNCTION FET AT LOW DRAIN CURRENTS

[1] LOW-LEVEL CURRENTS IN INSULATED GATE FIELD-EFFECT TRANSISTORS [J]. SOLID-STATE ELECTRONICS, 1972, 15 (03) : 293 - +

[2] LIMITATION OF PROPERTIES OF FIELD-EFFECT TRANSISTORS [J]. PROCEEDINGS OF THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 1966, 54 (01): : 82 - &

[3] JOHNSON EO, 1973, RCA REV, V34, P80

[4] KIM CK, 1970, IEEE T ELECTRON DEV, VED17, P120

[5] SUBTHRESHOLD DESIGN CONSIDERATIONS FOR INSULATED GATE FIELD-EFFECT TRANSISTORS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (02) : 55 - 60

[6] WEBER C, 1963, PHILIPS TECH REV, V24, P130

[1] LOW-LEVEL CURRENTS IN INSULATED GATE FIELD-EFFECT TRANSISTORS [J]. SOLID-STATE ELECTRONICS, 1972, 15 (03) : 293 - +

[2] LIMITATION OF PROPERTIES OF FIELD-EFFECT TRANSISTORS [J]. PROCEEDINGS OF THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 1966, 54 (01): : 82 - &

[3] JOHNSON EO, 1973, RCA REV, V34, P80

[4] KIM CK, 1970, IEEE T ELECTRON DEV, VED17, P120

[5] SUBTHRESHOLD DESIGN CONSIDERATIONS FOR INSULATED GATE FIELD-EFFECT TRANSISTORS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (02) : 55 - 60

[6] WEBER C, 1963, PHILIPS TECH REV, V24, P130