A DECODER WITH OR GATES FOR A JOSEPHSON HIGH-DENSITY MEMORY CIRCUIT

被引：4

作者：

IGARASHI, T

SUZUKI, H

HASUO, S

YAMAOKA, T

机构：

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1987年 / 22卷 / 01期

关键词：

D O I：

10.1109/JSSC.1987.1052675

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：85 / 91

页数：7

共 9 条

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[5] LOGIC GATES WITH SHAPED JOSEPHSON JUNCTIONS [J].

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NAKANISHI T, 1984, JPN J APPL PHYS 1, V23, P1002, DOI 10.1143/JJAP.23.1002

[7] A DIAGONAL ADDRESS GENERATOR FOR A JOSEPHSON MEMORY CIRCUIT [J].

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (01) :92-97

[8] A FALLING EDGE-TRIGGERED SINGLE SHOT PULSE-GENERATOR WITH JOSEPHSON DEVICES [J].

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