LOW-TEMPERATURE POLY-SI TFTS USING SOLID-PHASE CRYSTALLIZATION OF VERY THIN-FILMS AND AN ELECTRON-CYCLOTRON RESONANCE CHEMICAL VAPOR-DEPOSITION GATE INSULATOR

被引:50
作者
LITTLE, TW
TAKAHARA, K
KOIKE, H
NAKAZAWA, T
YUDASAKA, I
OHSHIMA, H
机构
[1] SEIKO EPSON CORPORATION, TFT Research Laboratory, Suwa, Nagano, 392, 3-3-5, Owa
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | 1991年 / 30卷 / 12B期
关键词
AMORPHOUS; POLYCRYSTALLINE; CRYSTALLINITY; SILICON; TFT; ECR; SOLID PHASE CRYSTALLIZATION; CHEMICAL VAPOR DEPOSITION; SIO2;
D O I
10.1143/JJAP.30.3724
中图分类号
O59 [应用物理学];
学科分类号
摘要
Low temperature (T less-than-or-equal-to 600-degrees-C) polycrystalline silicon thin film transistors (poly-Si TFTs) have been fabricated by solid phase crystallization (SPC) of amorphous silicon (a-Si) films deposited by low pressure chemical vapor deposition (LPCVD). These TFTs are distinguished by the very thin nature of the channel Si layer (25 nm) and the use of an SiO2 gate insulator deposited by electron cyclotron resonance chemical vapor deposition (ECR-CVD). The present process eliminates the need for hydrogenation and produces mobilities greater than 20 cm2/V.s and on/off current ratios greater than 10(7).
引用
收藏
页码:3724 / 3728
页数:5
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