WAFER CHARGING MONITORED BY HIGH-FREQUENCY AND QUASI-STATIC C-V MEASUREMENTS

被引：1

作者：

EN, B

CHEUNG, NW

机构：

[1] Plasma Assisted Materials Processing Laboratory, Department of Electrical Engineering and Computer Science, University of California, Berkeley

来源：

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION B-BEAM INTERACTIONS WITH MATERIALS AND ATOMS | 1993年 / 74卷 / 1-2期

关键词：

D O I：

10.1016/0168-583X(93)95067-F

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

A combined high frequency and quasi-static C-V technique is used to monitor wafer charging of MOS structures during plasma immersion ion implantation (PIII). The test chip used consists of MOS capacitors spanning over five decades of area (25 mum2 to 4 x 10(6) mum2). Measured interface trap density (Q(it)) is found to be dependent exponentially on plasma exposure time and linearly on the plasma ion density. The PIII pulsed bias voltage has no effect on wafer charging.

引用

页码：311 / 313

页数：3

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