STRESS AND CURRENT INDUCED VOIDING IN PASSIVATED METAL LINES

Thermal stress and current induced damage processes may well determine the ultimate limit for the achievable line widths in microelectronic circuits. According to our current understanding, thermal stresses cause void nucleation during cool-down from high temperature process steps. The voids may continue to grow during subsequent storage. The application of an electrical current may lead to further void growth, as well as migration and coalescence of voids. A recently developed model provides the framework for improved reliability assessments, including the effects of statistics, as well as for the development of remedies.