LATCHUP MODEL FOR THE PARASITIC P-N-P-N PATH IN BULK CMOS

被引：28

作者：

FANG, RCY ^{[1
]}

MOLL, JL ^{[1
]}

机构：

[1] HEWLETT PACKARD CO,HEWLETT PACKARD LAB,PALO ALTO,CA 94304

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1984年 / 31卷 / 01期

关键词：

D O I：

10.1109/T-ED.1984.21484

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：113 / 120

页数：8

共 15 条

[1] NEUTRON-IRRADIATION FOR PREVENTION OF LATCH-UP IN MOS INTEGRATED-CIRCUITS [J].

ADAMS, JR ;

SOKEL, RJ .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1979, 26 (06) :5069-5073

[2]

DAS MB, 1961, IRE T ELECTRON DEV, VED8, P15

[3] PREVENTION OF CMOS LATCH-UP BY GOLD DOPING [J].

DAWES, WR ;

DERBENWICK, GF .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1976, 23 (06) :2027-2030

[4] DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].

DENNARD, RH ;

GAENSSLEN, FH ;

YU, HN ;

RIDEOUT, VL ;

BASSOUS, E ;

LEBLANC, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268

[5] 4-TERMINAL P-N-P-N-TRANSISTORS [J].

EBERS, JJ .

PROCEEDINGS OF THE INSTITUTE OF RADIO ENGINEERS, 1952, 40 (11) :1361-1364

[6]

ESTREICH DB, 1980, G2019 STANF U INT CI

[7]

GENTRY FE, 1964, SEMICONDUCTOR CONTRO

[8] LATCH-UP IN CMOS INTEGRATED-CIRCUITS [J].

GREGORY, BL ;

SHAFER, BD .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1973, NS20 (06) :293-299

[9]

HAUSER JR, 1967, FUNDAMENTALS SILICON, V2

[10]

KYOMASU M, 1978, T IECE JAPAN E, V61

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