HIGH-QUALITY STACKED CMOS INVERTER

被引：4

作者：

ZINGG, RP ^{[1
]}

HOFFLINGER, B ^{[1
]}

NEUDECK, GW ^{[1
]}

机构：

[1] PURDUE UNIV,SCH ELECT ENGN,W LAFAYETTE,IN 47907

来源：

IEEE ELECTRON DEVICE LETTERS | 1990年 / 11卷 / 01期

关键词：

D O I：

10.1109/55.46914

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new stacked CMOS technology is introduced with enhanced device performance and small geometries. Surface-channel mobilities are measured to be 700 cm2/V-s for bulk n-channel devices and 165 cm2/V-s for the top PMOS transistors. Excellent subthreshold slope of 100 mV/decade and leakage currents below 150-f A/μm channel width were measured for both device types. The low-impurity crystalline silicon film on top of the bulk devices is produced by local epitaxial overgrowth (LOG), an important alternative to recrystallized silicon films for three-dimensional CMOS circuits. The structure is planarized and requires only six masks with reduced processing time. © 1990 IEEE

引用

页码：9 / 11

页数：3

共 12 条

[1] 3-DIMENSIONAL IC TRENDS [J].