EPITAXIAL-GROWTH ON POROUS SI FOR A NEW BOND AND ETCHBACK SILICON-ON-INSULATOR

被引:61
作者
SATO, N
SAKAGUCHI, K
YAMAGATA, K
FUJIYAMA, Y
YONEHARA, T
机构
[1] Canon Incorporated, Device Development Center, Research and Development Headquarters, Kanagawa 254, 6770 Tamura, Hiratsuka
关键词
D O I
10.1149/1.2048698
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
A new bond and etchback silicon-on-insulator (SOI) has been proposed and demonstrated, in which epitaxial layers on porous Si are transferred by bonding and etching back porous Si. The key processes are epitaxial growth on porous Si and selective removal of porous Si. In the epitaxial layers over porous Si, the major defects are stacking faults, which can be reduced to 10(3) to 10(4)/cm(2) by raising the H-2 prebake temperature and lengthening the immersion time in diluted HF prior to the prebake. Bondable smooth surfaces were formed at growth temperatures below 900 degrees C. A highly selective etchant of HF-H2O2 was discovered and enabled us to etch off porous Si with a selectivity of 10(5), leaving behind epitaxial layers on the oxidized handle wafers. The rough as-etched SOI surface was smooth comparable to that of the commercially available bulk-polished wafer, and boron concentration in the SOI-Si layer was simultaneously decreased to similar to 1 x 10(16)/cm(3), by H-2 annealing. Finally, a uniform SOI layer of 507 nm +/-3% across a 5 in. wafer was achieved by this method.
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收藏
页码:3116 / 3122
页数:7
相关论文
共 18 条
[1]   STRESS IN OXIDIZED POROUS SILICON LAYERS [J].
BARLA, K ;
HERINO, R ;
BOMCHIL, G .
JOURNAL OF APPLIED PHYSICS, 1986, 59 (02) :439-441
[2]  
GODBEY D, 1991, ELECTROCHEMICAL SOC, P174
[3]  
GOSELE U, 1993, ELECTROCHEMICAL SOC, P395
[4]  
Herino R., 1984, Materials Letters, V2, P519, DOI 10.1016/0167-577X(84)90086-7
[5]   POROSITY AND PORE-SIZE DISTRIBUTIONS OF POROUS SILICON LAYERS [J].
HERINO, R ;
BOMCHIL, G ;
BARLA, K ;
BERTRAND, C ;
GINOUX, JL .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1987, 134 (8A) :1994-2000
[6]  
HUNT CE, 1991, 1ST P INT S SEM WAF, P165
[7]   CRYSTALLINE QUALITY OF SILICON LAYER FORMED BY FIPOS TECHNOLOGY [J].
IMAI, K ;
UNNO, H ;
TAKAOKA, H .
JOURNAL OF CRYSTAL GROWTH, 1983, 63 (03) :547-553
[8]   A NEW DIELECTRIC ISOLATION METHOD USING POROUS SILICON [J].
IMAI, K .
SOLID-STATE ELECTRONICS, 1981, 24 (02) :159-&
[9]   CMOS DEVICES FABRICATED ON BURIED SIO2 LAYERS FORMED BY OXYGEN IMPLANTATION INTO SILICON [J].
IZUMI, K ;
DOKEN, M ;
ARIYOSHI, H .
ELECTRONICS LETTERS, 1978, 14 (18) :593-594
[10]  
Lasky J. B., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P684