OPTICAL AND ELECTRON-BEAM LITHOGRAPHY FOR ELECTROLESS COPPER MULTILEVEL METALLIZATION

被引:2
作者
SHACHAMDIAMAND, Y [1 ]
ANGYAL, M [1 ]
DEDHIA, A [1 ]
NASIR, Q [1 ]
机构
[1] CORNELL UNIV,NATL NANOFABRICAT FACIL,ITHACA,NY 14853
来源
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | 1992年 / 10卷 / 06期
关键词
D O I
10.1116/1.585951
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Copper fine lines made by electroless deposition are investigated for multilevel metallization in ultra-large-scale integration technology. The results are presented using positive patterning, i.e., depositing copper on patterned areas by electroless deposition. Two techniques have been developed: (a) a nonplanar technique that produces 100 nm wide copper lines standing over an interlevel dielectric (ILD); and (b) a fully planar method that produces 0.5 mum copper lines buried in an ILD. Both electron beam and optical lithography processes were developed and are described for the nonplanar process. First, a single layer exposure by e-beam is described and second, a portable conformal mask (PCM) process with double exposure, the first by i-line stepper and the second by deep ultraviolet flood exposure. For the fully planar process, the PCM process was modified to produce a capped PCM process. By using two resists of different etch selectivity, an overhang structure was produced which prevented the base metal from being deposited on the sidewalls of the oxide trench. A trilayer resist structure and a single layer structure with isotropic overetch were also developed. Scanning electron microscope pictures of submicron lines are presented followed by a discussion of the problems and highlights of the individual processes.
引用
收藏
页码:2958 / 2961
页数:4
相关论文
共 7 条
[1]  
HU CK, 1986, 3RD P INT IEEE VLSI, P181
[2]   PRACTICING THE NOVOLAC DEEP-UV PORTABLE CONFORMABLE MASKING TECHNIQUE [J].
LIN, BJ ;
BASSOUS, E ;
CHAO, VW ;
PETRILLO, KE .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY, 1981, 19 (04) :1313-1319
[3]   SELECTIVE ELECTROLESS COPPER FOR VLSI INTERCONNECTION [J].
PAI, PL ;
TING, CH .
IEEE ELECTRON DEVICE LETTERS, 1989, 10 (09) :423-425
[4]  
PAI PL, 1989, 6TH P VLSI MULT INT, P258
[5]  
Paunovic M., 1968, PLATING, V55, P1161
[6]   PROCESS RELIABILITY CONSIDERATIONS OF PLANARIZATION WITH SPIN-ON-GLASS [J].
SHACHAMDIAMAND, Y ;
NACHUMOVSKY, Y .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1990, 137 (01) :190-196
[7]  
WONG SS, 1991, UNPUB S VLSI TECHNOL, P39