ANOMALOUS CAPACITANCE-VOLTAGE CHARACTERISTICS OF BF2-IMPLANTED AND RAPID THERMAL ANNEALED P+-POLYCRYSTALLINE SILICON GATE METAL-OXIDE-SEMICONDUCTOR STRUCTURES

Anomalous capacitance-voltage (C-V) characteristics of BF 2-implanted p+-polycrystalline silicon (polysilicon) gate metal-oxide-semiconductor (MOS) structures annealed by rapid thermal annealing (RTA) are reported for the first time. It is found that both high-frequency and quasi-static C-V curves exhibit an increased capacitance at the depletion and weak inversion regions, which increases with p+-polysilicon RTA drive-in durations. The quasi-static C-V curves show a gate bias dependence of the inversion capacitance which shows a distorted "plateau" (i.e., reduced inversion capacitance for a very narrow gate voltage range) in the strong inversion regions. These anomalous C-V characteristics are believed to be due to the penetrated B-F complexes which act as interface state and deep level defect centers.