A high-dielectric-constant insulator, Ta2Os (ε = 22), seems most promising as the dielectric of storage capacitors for low-power high-density DRAM’s beyond 4 Mb whose operation voltage is reduced from 5 V in 4-Mb DRAM’s, down to 3.3 V in 16-Mb DRAM’s, and 1.5 V in 64-Mb DRAM’s. This reduction requires a significant increase in the capacitance in addition to the shrinking of the memory cell area. In order to ensure the required capacitance for low-power DRAM’s beyond 4 Mb, three kinds of capacitor structures are proposed: a) poly-Si/SiO2/Ta2O5/SiO2/poly-Si or poly-Si/Si3N4/Ta2O5/SiO2/poly-Si (SIS), b) W/Ta2Os/SiO2/poly-Si (MIS), and c) W/Ta2O5/W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO2 thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAM’s having stacked capacitor cells (STC) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAM’s having STC by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors enable us to fabricate low-power high-density DRAM’s beyond 4 Mb using conventional fabrication processes at high temperatures up to 950°C. Utilizing the SIS structure, compatibility of the fabrication process of a storage capacitor using Ta2O5 film and the conventional DRAM fabrication processes is confirmed by successful application to the fabrication process of an experimental memory array with 1.5 µm 3.6 µm stacked-capacitor DRAM cells. © 1990 IEEE
