A STUDY OF DEEP-SUBMICRON MOSFET SCALING BASED ON EXPERIMENT AND SIMULATION

The scaling relationships among three fundamental quantities of deep-submicron MOSFET's, i.e., effective channel length L(eff), device speed g(m)/WCox, and drain-induced barrier lowering (DIBL) delta V-t/delta V-ds, are investigated using both device measurements and numerical simulations. It is found that these relationships can be expressed in power-law forms with excellent statistical significance for both experimental and simulation data samples. The dependence of these scaling relationships on two sets of device parameters is also investigated experimentally and confirmed by numerical simulations. These two sets of parameters are: 1) channel parameters-gate oxide thickness tot, threshold voltage V-t, and channel doping profile; and 2) source/drain parameters-junction depth x(j), parasitic resistance R(sd), and junction abruptness (e.g., ''halo'' doping structure). In the deep-submicron regime with L(eff) from 0.5 mu m down to sub-0.1 mu m, it is found that certain relationships among the three fundamental quantities are insensitive or ''universal'' with respect to particular subsets of device parameters. The relationship between g(m)/WCox and delta V-t/delta V-ds, with L(eff) as an implicit variable is found to be insensitive to t(ox), V-t, and channel doping profile within their respective experimental ranges. The trade-off between device performance (represented by g(m)/WCox) and short channel effect (represented by delta V-t/delta V-ds) is dominated by source/drain parameters x(j), R(sd) and junction abruptness, rather than channel parameters t(ox), V-t and channel doping profile. Also, the power coefficient relating delta V-t/delta V-ds to L(eff) is found to be insensitive to t(ox), V-t, and channel doping profile.