A 1-MBIT FULL-WAFER MOS RAM

[1] WAFER-SCALE INTEGRATION - FAULT-TOLERANT PROCEDURE [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1978, 13 (03) : 339 - 344

[2] BARSUHN H, 1977, 3RD EUR SOL STAT CIR, P79

[3] MEANS OF REDUCING CUSTOM LSI INTERCONNECTION REQUIREMENTS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1972, SC 7 (05) : 395 - &

[4] FAULT-TOLERANT 64K DYNAMIC RANDOM-ACCESS MEMORY [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (06) : 853 - 860

[5] EGAWA Y, 1979, REV ELEC COMMUN LAB, V27, P82

[6] EGAWA Y, 1979, ISSCC 79, P18

[7] ASSOCIATIVE LINEAR-ARRAY PROCESSOR [J]. IEEE TRANSACTIONS ON COMPUTERS, 1977, 26 (02) : 112 - 125

[8] DEFECT ANALYSIS AND YIELD DEGRADATION OF INTEGRATED-CIRCUITS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (03) : 96 - 103

[9] HSIA Y, 1979, 11TH C SOLID STATE D, P81

[10] NISHI I, 1979, REV ELEC COMMUN LAB, V27, P92

[1] WAFER-SCALE INTEGRATION - FAULT-TOLERANT PROCEDURE [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1978, 13 (03) : 339 - 344

[2] BARSUHN H, 1977, 3RD EUR SOL STAT CIR, P79

[3] MEANS OF REDUCING CUSTOM LSI INTERCONNECTION REQUIREMENTS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1972, SC 7 (05) : 395 - &

[4] FAULT-TOLERANT 64K DYNAMIC RANDOM-ACCESS MEMORY [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (06) : 853 - 860

[5] EGAWA Y, 1979, REV ELEC COMMUN LAB, V27, P82

[6] EGAWA Y, 1979, ISSCC 79, P18

[7] ASSOCIATIVE LINEAR-ARRAY PROCESSOR [J]. IEEE TRANSACTIONS ON COMPUTERS, 1977, 26 (02) : 112 - 125

[8] DEFECT ANALYSIS AND YIELD DEGRADATION OF INTEGRATED-CIRCUITS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (03) : 96 - 103

[9] HSIA Y, 1979, 11TH C SOLID STATE D, P81

[10] NISHI I, 1979, REV ELEC COMMUN LAB, V27, P92