DESIGN AND EVALUATION OF ION-IMPLANTED CMOS STRUCTURES

被引：4

作者：

MOTAMEDI, ME

TAM, KY

STECKL, AJ

机构：

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1980年 / 27卷 / 03期

关键词：

D O I：

10.1109/T-ED.1980.19902

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：578 / 583

页数：6

共 9 条

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[5] COMPATIBLE NMOS, CMOS METAL GATE PROCESS [J].

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[6] INTERPRETATION OF SURFACE AND BULK EFFECTS USING PULSED MIS CAPACITOR [J].

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GULDBERG, J .

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[7]

STECKL AJ, 1978, 1978 P INT C CHARG C, P2

[8]

STECKL AJ, 1979, APPL PHYS LETT, V15, P537

[9]

ZAININGER KH, 1970, SOLID STATE TECH JUN

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