SIGE-CHANNEL HETEROJUNCTION P-MOSFETS

被引:182
作者
VERDONCKTVANDEBROEK, S
CRABBE, EF
MEYERSON, BS
HARAME, DL
RESTLE, PJ
STORK, JMC
JOHNSON, JB
机构
[1] IBM CORP,THOMAS J WATSON RES CTR,DIV RES,YORKTOWN HTS,NY 10598
[2] IBM CORP,DIV MICROELECTR,ESSEX JCT,VT 05452
关键词
D O I
10.1109/16.259625
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n(+) polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 mu m channel lengths and are preferable to p(+) polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n(+)-gate modulation-doped Sice p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm(2)/V.s at 300 K and 980 cm(2)/V.s at 82 K are obtained.
引用
收藏
页码:90 / 101
页数:12
相关论文
共 36 条
[1]  
Aoki M., 1990, International Electron Devices Meeting 1990. Technical Digest (Cat. No.90CH2865-4), P939, DOI 10.1109/IEDM.1990.237087
[2]   LOW-TEMPERATURE DEPOSITION OF HIGH-QUALITY SILICON DIOXIDE BY PLASMA-ENHANCED CHEMICAL VAPOR-DEPOSITION [J].
BATEY, J ;
TIERNEY, E .
JOURNAL OF APPLIED PHYSICS, 1986, 60 (09) :3136-3145
[3]   A HIGH-PERFORMANCE 0.25-MU-M CMOS TECHNOLOGY .1. DESIGN AND CHARACTERIZATION [J].
CHANG, WH ;
DAVARI, B ;
WORDEMAN, MR ;
TAUR, Y ;
HSU, CCH ;
RODRIGUEZ, MD .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (04) :959-966
[4]  
Daembkes H., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P768
[5]   A HIGH-PERFORMANCE 0.25-MU-M CMOS TECHNOLOGY .2. TECHNOLOGY [J].
DAVARI, B ;
CHANG, WH ;
PETRILLO, KE ;
WONG, CY ;
MOY, D ;
TAUR, Y ;
WORDEMAN, MR ;
SUN, JYC ;
HSU, CCH ;
POLCARI, MR .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (04) :967-975
[6]  
GANIN E, 1989, MATER RES SOC SYMP P, V128, P635
[7]   HOLE MOBILITY ENHANCEMENT IN MOS-GATED GEXSI1-X/SI HETEROSTRUCTURE INVERSION-LAYERS [J].
GARONE, PM ;
VENKATARAMAN, V ;
STURM, JC .
IEEE ELECTRON DEVICE LETTERS, 1992, 13 (01) :56-58
[8]   HOLE CONFINEMENT IN MOS-GATED GEXSI1-X/SI HETEROSTRUCTURES [J].
GARONE, PM ;
VENKATARAMAN, V ;
STURM, JC .
IEEE ELECTRON DEVICE LETTERS, 1991, 12 (05) :230-232
[9]   HIGH-TRANSCONDUCTANCE N-TYPE SI/SIGE MODULATION-DOPED FIELD-EFFECT TRANSISTORS [J].
ISMAIL, K ;
MEYERSON, BS ;
RISHTON, S ;
CHU, J ;
NELSON, S ;
NOCERA, J .
IEEE ELECTRON DEVICE LETTERS, 1992, 13 (05) :229-231
[10]   A GATE-QUALITY DIELECTRIC SYSTEM FOR SIGE METAL-OXIDE-SEMICONDUCTOR DEVICES [J].
IYER, SS ;
SOLOMON, PM ;
KESAN, VP ;
BRIGHT, AA ;
FREEOUF, JL ;
NGUYEN, TN ;
WARREN, AC .
IEEE ELECTRON DEVICE LETTERS, 1991, 12 (05) :246-248