MULTICHIP THIN-FILM TECHNOLOGY ON SILICON

被引：8

作者：

JOHNSON, RW ^{[1
]}

PHILLIPS, TL ^{[1
]}

JAEGER, RC ^{[1
]}

HAHN, SF ^{[1
]}

BURDEAUX, DC ^{[1
]}

机构：

[1] DOW CHEM USA,MAT SCI & DEV LAB,MIDLAND,MI 48674

来源：

IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1989年 / 12卷 / 02期

关键词：

Integrated Circuits; Monolithic; -; Metallizing; Substrates--Etching;

D O I：

10.1109/33.31423

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A novel hybrid technique that uses pretested integrated circuits mounted into holes etched in a silicon wafer has been developed. The chips are interconnected with planar, thin-film metallization. This approach achieves near-wafer-scale-integration density, while allowing the use of separately fabricated and tested devices. Test wafers with three monolithic chips and one chip mounted in a hole were fabricated as proof of concept. The key processes developed included fabrication of metallized and pattered wafers with etched holes, mounting of die in etched holes with planar topside topology, and deposition and patterning of the interlevel dielectric and metal links. An organic resin derived from benzocyclobutene was evaluated as the interlevel dielectric. Wafers were thermally cycled to evaluate the compatibility of the materials and the process. No cracks or chip movement were observed after 50 cycles from -25°C to + 85°C.

引用

页码：185 / 194

页数：10

共 41 条

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