AN ACCURATE DESIGN METHOD OF BIPOLAR-DEVICES USING A TWO-DIMENSIONAL DEVICE SIMULATOR

被引:7
作者
TOMIZAWA, M
KITAZAWA, H
YOSHII, A
HORIGUCHI, S
SUDO, T
机构
关键词
D O I
10.1109/T-ED.1981.20502
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
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页码:1148 / 1153
页数:6
相关论文
共 12 条
[1]   2-DIMENSIONAL SEMICONDUCTOR ANALYSIS USING FINITE-ELEMENT METHOD [J].
ADACHI, T ;
YOSHII, A ;
SUDO, T .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (07) :1026-1031
[2]   MERGED-TRANSISTOR LOGIC (MTL) - LOW-COST BIPOLAR LOGIC CONCEPT [J].
BERGER, HH ;
WIEDMANN, SK .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1972, SC 7 (05) :340-&
[3]   SUBSTRATE FED LOGIC [J].
BLATT, V ;
WALSH, PS ;
KENNEDY, LW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, 10 (05) :336-342
[4]  
GAUER SP, 1979, IEEE J SOLID STATE C, V14, P337
[5]   AN INTEGRAL CHARGE CONTROL MODEL OF BIPOLAR TRANSISTORS [J].
GUMMEL, HK ;
POON, HC .
BELL SYSTEM TECHNICAL JOURNAL, 1970, 49 (05) :827-+
[7]   2-DIMENSIONAL MATHEMATICAL-MODEL OF INSULATED-GATE FIELD-EFFECT TRANSISTOR [J].
MOCK, MS .
SOLID-STATE ELECTRONICS, 1973, 16 (05) :601-609
[8]  
SCHARFETTER DL, 1969, IEEE T ELECTRON DEVI, V16, P67
[9]  
SHOCKLEY W, 1952, PHYS REV, V87, P836
[10]   PN-PRODUCT IN SILICON [J].
SLOTBOOM, JW .
SOLID-STATE ELECTRONICS, 1977, 20 (04) :279-283