SIMULATION AND OPTIMIZATION OF BINARY FULL-ADDER CELLS IN RAPID SINGLE FLUX QUANTUM LOGIC

This paper considers the design of a binary carry full-adder cell employing the logic gates and buffers belonging to the RSFQ logic family. We have taken advantage of the unique properties of RSFQ pulse logic to realize two designs: one using two logic gates and a toggle flip-flop in two stages of logic, the other using two logic gates in one stage of logic. We have determined the parameter margins of the two full-adder cells and optimized them to obtain critical margins approaching +/- 30%. Simulations of the full-adder cells have revealed critical delays and maximum clock frequencies of 58 ps and 17 GHz and 33 ps and 30 GHz, respectively.