MULTICHIP PACKAGING FOR VERY-HIGH-SPEED DIGITAL-SYSTEMS

High-speed computing systems are limited by integrated circuit (IC) packaging technology. For system speed and compactness, IC's should be bonded in close proximity; however, this leads to heat-dissipation problems with conventional packaging. Residual inductance in chip-to-board connections also limits system speed. A packaging technology is being developed for very-high-speed, compact, and rugged computing systems, which is particularly well suited to high-power and high-I/O systems. A complete package consists of IC's bonded to a silicon circuit board (SiCB) which is, in turn, bonded to a microchannel heat-sink. The thin-film, eutectic bond between silicon dice and the SiCB provides intimate thermal and mechanical contact. The SiCB provides speed-of-light interconnect between IC's using SiO2 as the dielectric and copper metallization. A novel electrochemical metal planarization process is used in applications requiring multiple levels of interconnection on the silicon circuit board. Laser patterning permits chip-to-SiCB interconnect to be fabricated directly on the vertical walls of attached die, which results in higher I/O density and better electrical characteristics than allowed by wire bonding or tape automated bonding (TAB). Incorporation of the microchannel heat-sink reduces overall package thermal resistance per unit area by a factor of more than 50 compared to conventional technology. Memory modules have been produced with the technology and tested according to US space qualification procedures. Enhanced thermal-shock tests (500 K temperature change, 10 s cycle time) have demonstrated the ruggedness of the technology. © 1990.