学术探索
学术期刊
新闻热点
数据分析
智能评审

HIGH-PERFORMANCE ULTRATHIN SOI MOSFETS OBTAINED BY LOCALIZED OXIDATION

被引：6
作者：
FAYNOT, O
GIFFARD, B
机构：
[1] LETI CEA- Technologies Avancées, 38041 Grendole, DMEL-CENG
来源：
IEEE ELECTRON DEVICE LETTERS | 1994年 / 15卷 / 05期
关键词：
D O I：
10.1109/55.291595
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we present a new and simple method to process ultrathin fully depleted SOI MOSFET's. Series resistance problems in the full-wafer thinning method are presented and compared with our locally thinned process. Device design of the method is also discussed in terms of current level. The comparison of different process architectures allows us to define the best design rules for these transistors. To validate the method, experimental characteristics of locally thinned accumulation-mode MOSFET's are presented.
引用
收藏
页码：175 / 177
页数：3
相关论文
共 8 条
[1]   HOT-ELECTRON EFFECTS IN SILICON-ON-INSULATOR N-CHANNEL MOSFET [J].
COLINGE, JP .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (10) :2173-2177
[2]   INVESTIGATION OF THE INFLUENCE OF THE FILM THICKNESS IN ACCUMULATION-MODE FULLY-DEPLETED SIMOX MOSFETS [J].
FAYNOT, O ;
AUBERTONHERVE, AJ ;
CRISTOLOVEANU, S .
MICROELECTRONIC ENGINEERING, 1992, 19 (1-4) :807-810
[3]   A LATCH PHENOMENON IN BURIED N-BODY SOI NMOSFET [J].
GAUTIER, J ;
AUBERTONHERVE, AJ .
IEEE ELECTRON DEVICE LETTERS, 1991, 12 (07) :372-374
[4]  
Hisamoto D., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P829, DOI 10.1109/IEDM.1992.307485
[5]  
OMURA Y, 1983, IEEE, V30
[6]   CALCULATED THRESHOLD-VOLTAGE CHARACTERISTICS OF AN XMOS TRANSISTOR HAVING AN ADDITIONAL BOTTOM GATE [J].
SEKIGAWA, T ;
HAYASHI, Y .
SOLID-STATE ELECTRONICS, 1984, 27 (8-9) :827-828
[7]   INCREASED DRAIN SATURATION CURRENT IN ULTRA-THIN SILICON-ON-INSULATOR (SOI) MOS-TRANSISTORS [J].
STURM, JC ;
TOKUNAGA, K ;
COLINGE, JP .
IEEE ELECTRON DEVICE LETTERS, 1988, 9 (09) :460-463
[8]  
YAMAGUCHI Y, 1992, IEEE T ELECTRON DEVI, V39
1