25 GBIT/S DECISION CIRCUIT, 34 GBIT/S MULTIPLEXER, AND 40 GBIT/S DEMULTIPLEXER IC IN SELECTIVE EPITAXIAL SI BIPOLAR TECHNOLOGY

被引：10

作者：

FELDER, A ^{[1
]}

STENGL, R ^{[1
]}

HAUENSCHILD, J ^{[1
]}

REIN, HM ^{[1
]}

MEISTER, TF ^{[1
]}

机构：

[1] RUHR UNIV BOCHUM,AG HALBLEITERBAUELEMENTE,W-4630 BOCHUM,GERMANY

来源：

ELECTRONICS LETTERS | 1993年 / 29卷 / 06期

关键词：

INTEGRATED CIRCUITS; HIGH-SPEED BIPOLAR DEVICES;

D O I：

10.1049/el:19930351

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0-8 mum lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.

引用

页码：525 / 527

页数：3

共 6 条

[1]

FELDER A, 1993, FEB ISSCC 93 SAN FRA

[2] DEMONSTRATION OF RETIMING CAPABILITY OF SILICON BIPOLAR TIME-DIVISION MULTIPLEXER OPERATING TO 24 GBIT/S [J].

HAUENSCHILD, J ;

REIN, HM ;

MCFARLAND, W ;

DOERNBERG, J ;

PETTENGILL, D .

ELECTRONICS LETTERS, 1991, 27 (11) :978-979

[3]

HAUENSCHILD J, 1992, OCT BIP CIRC TECHN M, P151

[4]

MEISTER TF, 1992, DEC P IEDM 92 SAN FR, P401

[5] 30 GBIT/S MULTIPLEXER AND DEMULTIPLEXER ICS IN SILICON BIPOLAR TECHNOLOGY [J].

REIN, HM ;

HAUENSCHILD, J ;

MOLLER, M ;

MCFARLAND, W ;

PETTENGILL, D ;

DOERNBERG, J .

ELECTRONICS LETTERS, 1992, 28 (01) :97-99

[6]

REIN HM, 1992, GIGAHERTZ 92

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