DEMONSTRATION OF RETIMING CAPABILITY OF SILICON BIPOLAR TIME-DIVISION MULTIPLEXER OPERATING TO 24 GBIT/S

被引：10

作者：

HAUENSCHILD, J ^{[1
]}

REIN, HM ^{[1
]}

MCFARLAND, W ^{[1
]}

DOERNBERG, J ^{[1
]}

PETTENGILL, D ^{[1
]}

机构：

[1] HEWLETT PACKARD CO,PALO ALTO,CA 94304

来源：

ELECTRONICS LETTERS | 1991年 / 27卷 / 11期

关键词：

INTEGRATED CIRCUITS; MULTIPLEXERS;

D O I：

10.1049/el:19910610

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The retiming capability of a high-speed silicon bipolar time-division multiplexer IC is demonstrated. At an output data rate of 20 Gbit/s a clock phase margin of 150-degrees was measured. The maximum data rate of 24 Gbit/s is the best experimental value reported for silicon multiplexers.

引用

页码：978 / 979

页数：2

共 4 条

[1] 20 GBIT/S TIME-DIVISION MULTIPLEXER IC IN SILICON BIPOLAR TECHNOLOGY [J].