23 GBIT/S SI BIPOLAR DECISION CIRCUIT CONSISTING OF 2J GBIT/S MUX AND DEMUX ICS

被引：6

作者：

REIN, HM ^{[1
]}

HAUENSCHILD, J ^{[1
]}

MCFARLAND, W ^{[1
]}

PETTENGILL, D ^{[1
]}

机构：

[1] HEWLETT PACKARD CO,PALO ALTO,CA 94304

来源：

ELECTRONICS LETTERS | 1991年 / 27卷 / 11期

关键词：

INTEGRATED CIRCUITS; MULTIPLEXERS;

D O I：

10.1049/el:19910608

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A parallel operating decision circuit was built from high-speed MUX and DEMUX ICs both realised in a 0.8-mu-m selfaligned single-polysilicon bipolar technology. The circuit operates up to 23 Gbit/s at a clock phase margin of 207-degrees. This is the highest data rate reported for a decision circuit in any IC technology.

引用

收藏

页码：974 / 976

页数：3

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