PARALLEL STRUCTURE FOR SIGNED-NUMBER MULTIPLICATION AND ADDITION

被引：8

作者：

DEMORI, R

SERRA, A

机构：

[1] POLITECN TORINO, IST ELETTROTEC, TURIN, ITALY

[2] IST ELETTROTEC NAZL GALILEO FERRARIS, TURIN, ITALY

来源：

关键词：

D O I：

10.1109/T-C.1972.223525

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：1453 / 1454

页数：2

共 7 条

[1] DESIGN FOR A FULL MULTIPLIER [J].

DEAN, KJ .

PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON, 1968, 115 (11) :1592-&

[2] CELLULAR MULTIPLIER FOR SIGNED BINARY NUMBERS [J].

DEEGAN, ID .

[3] SUGGESTION FOR AN IC FAST PARALLEL MULTIPLIER [J].

DEMORI, R .

[4]

DEMORI R, 1969, SEP P INT S DES APPL, P1076

[5]

GEX A, 1971, ELECTRON LETT, V7, P436

GUILD, HH .

[7] ITERATIVE ARRAY FOR MULTIPLICATION OF SIGNED BINARY NUMBERS [J].

MAJITHIA, JC ;

KITAI, R .