A STATIC RANDOM-ACCESS MEMORY CELL USING A DOUBLE EMITTER RESONANT-TUNNELING HOT-ELECTRON TRANSISTOR FOR GIGABIT-PLUS MEMORY APPLICATIONS

被引:18
作者
MORI, T
MUTO, S
TAMURA, H
YOKOYAMA, N
机构
[1] Fujitsu Limited, Atsugi, 243-01
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | 1994年 / 33卷 / 1B期
关键词
SRAM CELL; DOUBLE EMITTER; RHET; RESONANT TUNNELING; NDR; HYSTERESIS LOOP; BISTABLE;
D O I
10.1143/JJAP.33.790
中图分类号
O59 [应用物理学];
学科分类号
摘要
This paper describes our research on quantum memory devices having a single transistor structure similar to that of a double-emitter resonant-tunneling hot electron transistor (RHET). Its prototype 2 x 2 bit cell array was fabricated and operated at room temperature. The device used in the prototype cell had no current gain, however, and required other active devices to build static random access memory (SRAM) peripheral circuits such as a decoder and senseamplifier. We also report recent advances in the memory cell made using a double-emitter RHET which has a current gain of 8 at 77 K-suitable for logic circuits peripheral to our memory cell array. The cell's small size shows promise for use in large scale memory application.
引用
收藏
页码:790 / 793
页数:4
相关论文
共 12 条
[1]   RESONANT TUNNELING DEVICES WITH MULTIPLE NEGATIVE DIFFERENTIAL RESISTANCE AND DEMONSTRATION OF A 3-STATE MEMORY CELL FOR MULTIPLE-VALUED LOGIC APPLICATIONS [J].
CAPASSO, F ;
SEN, S ;
CHO, AY ;
SIVCO, D .
IEEE ELECTRON DEVICE LETTERS, 1987, 8 (07) :297-299
[2]   A PSEUDOMORPHIC IN0.53GA0.47AS ALAS RESONANT TUNNELING BARRIER WITH A PEAK-TO-VALLEY CURRENT RATIO OF 14 AT ROOM-TEMPERATURE [J].
INATA, T ;
MUTO, S ;
NAKATA, Y ;
SASA, S ;
FUJII, T ;
HIYAMIZU, S .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 1987, 26 (08) :L1332-L1334
[3]  
ISOBE M, 1984, ISSCC, P214
[4]  
MORI T, 1992, 19TH PINT S GAAS REL, P365
[5]   9-STATE RESONANT TUNNELING DIODE MEMORY [J].
SEABAUGH, AC ;
KAO, YC ;
YUAN, HT .
IEEE ELECTRON DEVICE LETTERS, 1992, 13 (09) :479-481
[6]   RESONANT TUNNELING DEVICE WITH MULTIPLE NEGATIVE DIFFERENTIAL RESISTANCE - DIGITAL AND SIGNAL-PROCESSING APPLICATIONS WITH REDUCED CIRCUIT COMPLEXITY [J].
SEN, S ;
CAPASSO, F ;
CHO, AY ;
SIVCO, D .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (10) :2185-2191
[7]   A MULTIPLE-STATE MEMORY CELL BASED ON THE RESONANT TUNNELING DIODE [J].
SODERSTROM, J ;
ANDERSSON, TG .
IEEE ELECTRON DEVICE LETTERS, 1988, 9 (05) :200-202
[8]  
SUZUKI M, 1991, INT SOL STAT CIRC C, P48
[9]   LOGIC-CIRCUITS USING RESONANT-TUNNELING HOT-ELECTRON TRANSISTORS (RHETS) [J].
TAKATSU, M ;
IMAMURA, K ;
OHNISHI, H ;
MORI, T ;
ADACHIHARA, T ;
MUTO, S ;
YOKOYAMA, N .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (10) :1428-1430
[10]  
WATANABE Y, 1992, 1992 INT EL DEV M SA, P475