EFFECT OF RTP FURNACE PROCESSING ON THE MINORITY-CARRIER LIFETIME IN VERY THIN OXIDE MOS CAPACITORS

被引：1

作者：

FONSECA, L

CAMPABADAL, F

机构：

[1] Centre Nacional de Microelectrǹoica, CSIC, 08193 Bellaterra, Campus Universitat Autonoma Barcelona

来源：

SOLID-STATE ELECTRONICS | 1994年 / 37卷 / 01期

关键词：

D O I：

10.1016/0038-1101(94)90114-7

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper the effects of oxidation and annealing processes on the minority carrier lifetime in silicon have been investigated. Using the pulsed MOS capacitor method a comparison of two methods used to grow very thin SiO2 layers, conventional furnace processing and rapid thermal processing (RTP), has been carried out. It is shown that those substrates which underwent RT high temperature steps sustained less damage, probably due to the lower contamination that results from this method.

引用

收藏

页码：115 / 117

页数：3

相关论文

共 11 条

[1] ON THE ORIGIN OF RAPID THERMAL-PROCESS INDUCED RECOMBINATION CENTERS IN SILICON [J].

EICHHAMMER, W ;

QUAT, VT ;

SIFFERT, P .

JOURNAL OF APPLIED PHYSICS, 1989, 66 (08) :3857-3865

[2] DEPENDENCE OF MINORITY-CARRIER BULK GENERATION IN SILICON MOS STRUCTURES ON HCL CONCENTRATION IN AN OXIDIZING AMBIENT [J].

ESQUEDA, PD ;

DAS, MB .

SOLID-STATE ELECTRONICS, 1980, 23 (07) :741-746

[3] A COMPARISON OF RTO AND FURNACE SIO2 TIME-ZERO-BREAKDOWN CHARACTERISTICS [J].

FONSECA, L ;

CAMPABADAL, F .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (08) :1743-1747

[4] ON DETERMINATION OF MINORITY CARRIER LIFETIME FROM TRANSIENT RESPONSE OF AN MOS CAPACITOR [J].

HEIMAN, FP .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1967, ED14 (11) :781-+

[5] MINORITY-CARRIER LIFETIME - CORRELATION WITH IC PROCESS PARAMETERS [J].

HUFF, HR ;

CHIU, TL .

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1979, 126 (07) :1142-1147

[6] THE EFFECT OF HIGH-TEMPERATURE ANNEALING ON THE SPATIAL VARIATION OF BULK LIFETIME NEAR THE SI-SIO2 INTERFACE [J].

MANCHANDA, L ;

VASI, J ;

BHATTACHARYYA, AB .

SOLID-STATE ELECTRONICS, 1980, 23 (10) :1015-1020

[7] AN EXPERIMENTAL 4-MBIT CMOS EEPROM WITH A NAND-STRUCTURED CELL [J].

MOMODOMI, M ;

ITOH, Y ;

SHIROTA, R ;

IWATA, Y ;

NAKAYAMA, R ;

KIRISAWA, R ;

TANAKA, T ;

ARITOME, S ;

ENDOH, T ;

OHUCHI, K ;

MASUOKA, F .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1238-1243

[8] SINGLE-WAFER INTEGRATED SEMICONDUCTOR-DEVICE PROCESSING [J].

MOSLEHI, MM ;

CHAPMAN, RA ;

WONG, M ;

PARANJPE, A ;

NAJM, HN ;

KUEHNE, J ;

YEAKLEY, RL ;

DAVIS, CJ .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (01) :4-32

[9] RAPID THERMAL-PROCESSING OF THIN GATE DIELECTRICS - OXIDATION OF SILICON [J].

NULMAN, J ;

KRUSIUS, JP ;

GAT, A .

IEEE ELECTRON DEVICE LETTERS, 1985, 6 (05) :205-207

[10] DEPENDENCE OF INTERFACE STATE DENSITY ON SILICON THERMAL-OXIDATION PROCESS VARIABLES [J].

RAZOUK, RR ;

DEAL, BE .

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1979, 126 (09) :1573-1581